Computer chips are often connected to an underlying substrate using a series of solder balls, solder bumps, or other solder joints or the like (often called first level interconnect solder bumps) that are positioned between the chip and the substrate and then heated to the point where the solder reflows. During chip attach there is a significant thermal expansion mismatch between the substrate and the chip (also referred to herein as a die) because of the large difference in their coefficients of thermal expansion (CTE). A typical organic substrate has a CTE that is perhaps five or six times greater than the CTE of a silicon die. Accordingly, when the die is placed on the substrate and heated to the solder reflow temperature, the expansion experienced by the substrate is considerably larger than that experienced by the die. As a result of this mismatch in thermal expansion rates the die is very often warped, bent, or otherwise deformed when the die and the substrate are later cooled to room temperature and the solder has solidified. The thermal expansion mismatch also causes significant shear stresses in the first level interconnect solder bumps as well as stresses in the die interconnect layers. These stresses are increased when the substrates are relatively thick, relatively stiff (e.g., have a relatively high elastic modulus), or have locally high copper densities near the solder bumps. All of these stresses can cause cracking of the solder bumps following chip attach.
Relaxation of substrate design rules, such as a change from solder mask defined pads to metal defined pads, have been used in an attempt to overcome the solder bump cracking problem. Such changes, however, are often accompanied by a deterioration in electrical performance. Other attempts to alleviate solder bump cracking include the local modification of substrate copper densities and substrate solder resist openings. These, however, are point solutions that cannot always be deployed. Major processing changes designed to circumvent the problem are in many cases similarly impractical. Accordingly, there exists a need for a structure capable of reducing stresses and strains in solder interconnect materials, and in the dies and substrates with which they are associated, that is not burdened with the foregoing and other shortcomings of existing attempted solutions.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention. The same reference numerals in different figures denote the same elements.
The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. Objects described herein as being “adjacent to” each other may be in physical contact with each other, in close proximity to each other, or in the same general region or area as each other, as appropriate for the context in which the phrase is used.